`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:08:46 04/13/2009 
// Design Name: 
// Module Name:    piperegIDEX 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module piperegIDEX(in1, in2, in3, in4, in5,in6,in7,in8,in9,in10,in11, clk, out1,out2,out3,out4,out5,out6,
							out7,out8,out9,out10,out11);
    input [31:0] in1;
    input [3:0] in2;
    input in3,clk;
    input in4,in6,in8,in9,in10,in11;
    input [31:0]in5,in7;
	 output [31:0] out1;
	 output [3:0] out2;
	 output out3,out4,out6,out8,out9,out10,out11;
	 output [31:0]out5,out7;
	 
	 reg [31:0] out1,out5,out7;
	 reg [3:0] out2;
	 reg out3,out4,out6,out8,out9,out10,out11;
	 
	 always @ (posedge clk)
	 begin
	 out1 = in1;
	 out2 = in2;
	 out3 = in3;
	 out4 = in4;
	 out5 = in5;
	 out6 = in6;
	 out7 = in7;
	 out8 = in8;
	 out9 = in9;
	 out10 = in10;
	 out11 = in11;
	 end
endmodule
